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The EVEX prefix (Enhanced vector extension) and corresponding coding scheme is an extension to the 32-bit x86 (IA-32) and 64-bit x86-64 (AMD64) instruction set architecture. EVEX is based on, but should not be confused with the MVEX prefix used by the Knights Corner processor. The EVEX scheme is a 4-byte extension to the VEX scheme which supports the AVX-512 instruction set and allows addressing new 512-bit ZMM registers and new 64-bit operand mask registers. ==Features== EVEX coding can address 8 operand mask registers, 16 general-purpose registers and 32 vector registers in 64-bit mode (otherwise, 8 general-purpose and 8 vector), and can support up to 4 operands. Like the VEX coding scheme, the EVEX prefix unifies existing opcode prefixes and escape codes, memory addressing and operand length modifiers of the x86 instruction set . The following features are carried over from the VEX scheme: * Direct encoding of three SIMD registers (XMM, YMM, or ZMM) as source operands (MMX or x87 registers are not supported); * Compacted REX prefix for 64-bit mode; * Compacted SIMD prefix (66H, F2H, F3H), escape opcode (0FH) and two-byte escape (0F38H, 0F3AH); * Less strict memory alignment requirements for memory operand EVEX also extends VEX with additional capabilities: * Extended SIMD register encoding: a total of 32 new 512-bit SIMD registers ZMM0-ZMM31 in 64-bit mode; * Operand mask encoding: 8 new 64-bit opmask registers k0-k7 for conditional execution and merging of destination operands; * Broadcasting from source to destination for instructions that take memory vector as a source operand: the second operand is broadcast before being used in the actual operation; * Direct embedded rounding control for instructions that operate on floating-point SIMD registers with rounding semantics; * Embedded exceptions control for floating-point instructions without rounding semantics; * Compressed displacement (DISP8 *N), new memory addressing mode to improve encoding density of instruction byte stream; the scale factor N depends on vector length and broadcast mode. For example, the EVEX encoding scheme allows conditional vector addition in the form of VADDPS zmm1 , zmm2, zmm3 where modifier next to the destination operand encodes the use of opmask register k1 for conditional processing and updates to destination, and modifier (encoded by EVEX.z) provides the two types of masking (merging and zeroing), with merging as default when no modifier is attached. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「EVEX prefix」の詳細全文を読む スポンサード リンク
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